Dynamic Voltage Scaling and Adaptive Body Bias for Energy-Efficient Ultra-Low Voltage CMOS VLSI Systems under Process Variations

Abstract

The development of ultra-low voltage (ULV) CMOS circuits for the Internet of Things (IoT), wearable electronics, wireless sensor networks, implantable biomedical devices, and edge computing has increased due to the increasing need for dependable and energy-efficient Very Large-Scale Integration (VLSI) systems. Sub-threshold and near-threshold operation dramatically lowers dynamic power consumption, but also degrades circuit performance and reliability by increasing propagation delay, leakage current, and sensitivity to process and temperature changes. This research suggests a hybrid adaptive power optimization system that combines Dynamic Voltage Scaling (DVS) and Adaptive Body Biasing (ABB) to address these issues. The suggested method simultaneously regulates the supply voltage based on workload needs and dynamically modifies the transistor body bias in accordance with process corners and temperature conditions.

CMOS logic circuits, such as an inverter, NAND gate, NOR gate, and complete adder developed in 45 nm CMOS technology using the Cadence Virtuoso Analog Design Environment, are used to assess the suggested framework. Multiple process corners (TT, SS, FF, FS, and SF), supply voltages between 0.25 V and 0.5 V, and temperatures between −20°C and 125°C are all simulated. Robustness against manufacturing-induced process changes is assessed using Monte Carlo analysis. Average power, leakage power, propagation delay, Power-Delay Product (PDP), and Energy-Delay Product (EDP) are used to evaluate performance. The results show that the suggested ABB-DVS architecture increases robustness, lowers leakage power, boosts energy efficiency, and offers a scalable solution for next-generation low-power CMOS VLSI systems.